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MVTX1100 9-Port Home PNA Packet Concentrator
Data Sheet Features
* * * * * 8 1/10 Mbps Serial ports direct interface with Home PNA PHY or 8 10/100 Mbps RMII ports Ideal for MDU (Multiple Dwelling Unit) application with Home PNA PHY 1 10/100 Mbps auto-negotiating MII/serial port (port 8) that can be used as uplink port Up to 8 port-based VLANs can be configured from EEPROM Internal 1 k MAC address table * Auto address learning Auto address aging * * * * *
November 2003
Ordering Information MVTX1100AL 208 Pin PQFP -40C to +85C Ability to support WinSock 2.0 and Windows 98 & Windows 2000 smart applications Transmit delay control capabilities Provides maximum delay guarantee (<1 ms)(Last bit in to first bit out) Supports mixed voice-data networks
Leading edge QoS capabilities provided based on 802.1 p and IP TOS/DS field 2 queues per output port Packet scheduling based on Weighted RoundRobin (WRR) Weighted Random Early Detection/Drop (WRED) to drop packets during traffic congestion 2 levels of packet drop provided
Support Concentrator mode Ports 0 & 1 can be trunked to provide a 2x1/10 Mbps link to another switch or server Utilizes a single low-cost external pipelined, SyncBurst SRAM (SBRAM) for buffer memory 56 k bytes or 512 k bytes (1 chip) External I2C EEPROM for power-up configuration Support external parallel port for configuration updates Optimized pin-out for easy board layout Packaged in a 208 PQFP
* * * *
* *
Supports both Full/Half duplex ports Full wire-speed layer 2 switching on all ports
S S R A M 1/10MB* Serial Interface
MVTX1100 9-Port Home PNA Packet Concentrator
10/100 MII CPU
Home PNA PHY
Home PNA PHY
8 Port Home PNA + 1-Port MII Switch
* also supports 10/100MB RMII Interface
Figure 1 - System Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
MVTX1100
Description
Data Sheet
The MVTX1100 is a fully integrated 9-port Ethernet packet concentrator designed to support Home Networking. It is ideal for Multiple Dwelling Units (MDU) application. The MVTX1100 provides features normally not associated with plug-and-play technology without requiring an external processor to facilitate their utilization. The MVTX1100 begins operating immediately at power-up, learning addresses automatically and forwarding packets at full wire speed to any of its 8 output ports or the uplink expansion port. At power-up, MVTX1100 configures itself from the EEPROM, and can then provide port trunking, port-based VLANs, and Quality of Service (QoS) capabilities, usually associated only with managed switches. The proprietary built-in intelligence of the MVTX1100 allows it to recognize and offer packet prioritization QoS. Packets are prioritized based on their layer 2 VLAN priority tag or layer 3 Type-Of Service/ Differentiated Services (TOS/DS) field. This priority can be defined as transmit and/or drop priority. The MVTX1100 can be used to create an 8-port unmanaged switch with one WAN router port by adding a CPU (ARM or MPC 850) connected to the additional MII port (port 8). The only external components needed for a low cost MDU system are the Home PNA physical layer transceivers and a single SBRAM per MVTX1100. Operating at 50 MHz internally, and with a 50 MHz interface to the external SBRAM, the MVTX1100 sustains full wire-speed switching on all 9 ports. When the system supports 8 ports of 1 M Home PNA PHY with the 10M Serial uplink, the system clock can be operated to 20 MHz and still achieve full wire-speed switching on all nine ports. The chip is packaged in a small 208 pin Plastic Quad Flat-Pak (PQFP) package.
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Zarlink Semiconductor Inc.
MVTX1100
MVTX1100 Physical Pinout
LA_[6] VSS L_A[5] L_A[4] L_A[3] L_A[18] VDD L_D[31] L_D[30] L_D[29] VSS (CORE) L_D[28] L_D[27] L_D[26] VDD L_D[25] L_D[24] L_D[23] L_D[22] VSS L_D[21] L_D[20] L_D[19] L_D[18] VDD (CORE) L_D[17] L_D[16] L_D[15] VSS L_D[14] L_D[13] L_D[12] L_D[11] VDD L_D[10] L_D[9] L_D[8] VSS (CORE) L_D[7] L_D[6] L_D[5] L_D[4] VDD L_D[3] L_D[2] L_D[1] VSS L_D[0] L_A[15] VDD (CORE) L_A[16] L_ADSC# 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 2 4 6 8 10 12
Data Sheet
L_A[7] L_A[8] VDD_CORE L_A[9] L_A[10] L_A[11] VSS L_A[12] L_A[13] L_A[14] VDD M0_CLS M0_LINK M0_DUPLEX M1_CLS M1_LINK M1_DUPLEX VSS (CORE) M0_TXEN M0_TXD M0_TXCLK M0_CRS_DV M0_RXD M0_RXCLK VDD M1_TXEN M1_TXD M1_TXCLK M1_CRS_DV M1_RXD M1_RXCLK VSS M2_TXEN M2_TXD M2_TXCLK M2_CRS_DV M2_RXD M2_RXCLK VDD (CORE) M3_TXEN M3_TXD M3_TXCLK M3_CRS_DV M3_RXD M3_RXCLK VSS (CORE) M2_CLS M2_LINK M2_DUPLEX M3_CLS M3_LINK M3_DUPLEX
156 154 152 150 148 146 144
+
Pin 1 I.D.
Buffer Mem Interface
14 16
142
140 138 136 134 132 130 128 126 124
20 22 24 26 28 30 32 34 36
RMII Port Interfaces
18
122 120
MII Port Interfaces
38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96
118 116 114 112 110 108 106
RMII Port Interfaces
98 100 102 104
L_OE# L_WE# VSS L_CLK VDD L_A[17] L_A[2] VSS SCLK VDD MIR_CTL[3] MIR_CTL[2] MIR_CTL[1] MIR_CTL[0] RSTIN# RSTOUT# VSS (CORE) T_MODE TSTOUT[7] TSTOUT[6] TSTOUT[5] TSTOUT[4] TSTOUT[3] TSTOUT[2] TSTOUT[1] TSTOUT[0] VDD (CORE) ACK DATA0 STROBE TRUNK_EN TEST# SDA SCL M_MDIO VSS M_MDC VDD M8_REFCLK VSS M8_SPEED M8_DUPLEX M8_LINK M8_TXD[3] M8_TXD[2] M8_TXD[1] M8_TXD[0] M8_TXEN VDD M8_TXCLK VSS (CORE) M8_RXD[3]
M4_CLS M4_LINK M4_DUPLEX M5_CLS M5_LINK M5_DUPLEX VDD M4_TXEN M4_TXD M4_TXCLK M4_CRS_DV M4_RXD M4_RXCLK VSS M5_TXEN M5_TXD M5_TXCLK M5_CRS_DV M5_RXD M5_RXCLK VDD (CORE) M6_TXEN M6_TXD M6_TXCLK M6_CRS_DV M6_RXD M6_RXCLK VSS (CORE) M7_TXEN M7_TXD M7_TXCLK M7_CRS_DV M7_RXD M7_RXCLK VDD M6_CLS M6_LINK M6_DUPLEX M7_CLS M7_LINK M7_DUPLEX VSS M_CLK VDD (CORE) M8_RXDV M8_COL VSS M8_RXCLK VDD M8_RXD[0] M8_RXD[1] M8_RXD[2]
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Zarlink Semiconductor Inc.
Config Interfaces
MVTX1100
Pin Reference Table Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 L_A[7] L_A[8] VDD (CORE) L_A[9] L_A[10] L_A[11] VSS L_A[12] L_A[13] L_A[14] VDD M0_CLS M0_LINK M0_DUPLEX M1_CLS M1_LINK M1_DUPLEX VSS (CORE) M0_TXEN M0_TXD/(M0_TXD[0])1 M0_TXCLK/(M0_TXD[1]) M0_CRS_DV M0_RXD/(M0_RXD[0]) M0_RXCLK/(M0_RXD[1]) VDD M1_TXEN M1_TXD/(M1_TXD[0]) M1_TXCLK/(M1_TXD[1]) M1_CRS_DV M1_RXD/(M1_RXD[0]) M1_RXCLK/(M1_RXD[1]) VSS M2_TXEN M2_TXD/(M2_TXD[0]) Pin Name 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 M2_TXCLK/M2_TXD[1]) M2_CRS_DV M2_RXD/(M2_RXD[0]) M2_RXCLK/ (M2_RXD[1]) VDD (CORE) M3_TXEN M3_TXD/(M3_TXD[0]) M3_TXCLK/(M3_TXD[1]) M3_CRS_DV M3_RXD/(M3_RXD[0]) M3_RXCLK/(M3_RXD[1]) VSS (CORE) M2_CLS M2_LINK M2_DUPLEX M3_CLS M3_LINK M3_DUPLEX M4_CLS M4_LINK M4_DUPLEX M5_CLS M5_LINK M5_DUPLEX VDD M4_TXEN M4_TXD/(M4_TXD[0]) M4_TXCLK/(M4_TXD[1]) M4_CRS_DV M4_RXD/(M4_RXD[0]) M4_RXCLK/(M4_RXD[1]) VSS M5_TXEN M5_TXD/(M5_TXD[0]) M5_TXCLK/M5_TXD[1]) 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 70 71 72 73 74 75 76
Data Sheet
M5_CRS_DV M5_RXD/(M5_RXD[0]) M5_RXCLK/ (M5_RXD[1]) VDD (CORE) M6_TXEN M6_TXD/(M6_TXD[0]) M6_TXCLK/ (M6_TXD[1]) M6_CRS_DV M6_RXD/(M6_RXD[0]) M6_RXCLK/ (M6_RXD1]) VSS (CORE) M7_TXEN M7_TXD/(M7_TXD[0]) M7_TXCLK/(M7_TXD[1]) M7_CRS_DV M7_RXD/(M7_RXD[0]) M7_RXCLK/(M7_RXD[1]) VDD M6_CLS M6_LINK M6_DUPLEX M7_CLS M7_LINK M7_DUPLEX VSS M_CLK VDD (CORE) M8_RXDV/S8_CRS_DV M8_COL/S8_COL VSS M8_RXCLK/S8_RXCLK VDD M8_RXD[0]/S8_RXD M8_RXD[1]
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Zarlink Semiconductor Inc.
MVTX1100
104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 M8_RXD[2] M8_RXD[3] VSS (CORE) M8_TXCLK/S8_TXCLK VDD M8_TXEN[0]/S8_TXEN M8_TXD[0]/S8_TXD M8_TXD[1] M8_TXD[2] M8_TXD[3] M8_LINK/S8_LINK M8_DUPLEX/S8_DUPLE X M8_SPEED VSS M8_REFCLK VDD M_MDC VSS M_MDIO SCL SDA TEST# TRUNK_ENABLE STROBE DATA0 ACK VDD (CORE) TSTOUT[0] TSTOUT[1] TSTOUT[2] TSTOUT[3] TSTOUT[4] TSTOUT[5] TSTOUT[6] TSTOUT[7] 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 T_MODE VSS (CORE) RSTOUT# RSTIN# (MIRROR_CONTROL[0]) (MIRROR_CONTROL[1]) (MIRROR_CONTROL[2]) (MIRROR_CONTROL[3]) VDD SCLK VSS L_A[2] L_A[17] VDD L_CLK VSS L_WE# L_OE# L_ADSC# L_A[16] VDD (CORE) L_A[15] L_D[0] VSS L_D[1] L_D[2] L_D[3] VDD L_D[4] L_D[5] L_D[6] L_D[7] VSS (CORE) L_D[8] L_D[9] L_D[10] 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Note 1:
Data Sheet
VDD L_D[11] L_D[12] L_D[13] L_D[14] VSS L_D[15] L_D[16] L_D[17] VDD (CORE) L_D[18] L_D[19] L_D[20] L_D[21] VSS L_D[22] L_D[23] L_D[24] L_D[25] VDD L_D[26] L_D[27] L_D[28] VSS (CORE) L_D[29] L_D[30] L_D[31] VDD L_A[18] L_A[3] L_A[4] L_A[5] VSS L_A[6]
Pin names inside ( ) indicate RMII pins for ports 0-7.
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Zarlink Semiconductor Inc.
MVTX1100
Data Sheet
S S R A M 10 MB Serial Interface
MVTX1100 Switch Chip 1-Port MII 10/100 8-Port 10 MB Serial
10/100 MII
PAL
10/100 RMII MVTX2604 Routing Switch 1 G GMII 24 10/100 Ports + 2-1 G Uplinks
Home PNA PHY
Home PNA PHY
. . .
Line Card
192+2 Port Switch MDU System 10 Mbps Serial Interface
S S R A M 1 MB Serial Interface
MVTX1100 8-Port 1 MB Serial
MVTX1100
10/100 MII
Home PNA PHY
Home PNA PHY
Line Card
64+1 Port Switch MDU System
Figure 2 - System Block Diagram (High Port Density MDU System)
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Zarlink Semiconductor Inc.
MVTX1100
Data Sheet
1k
Figure 3 - MVTX1100 Block Diagram
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Zarlink Semiconductor Inc.
MVTX1100
1.0 Functional Operation
Data Sheet
The MVTX1100 was designed to provide a cost-effective layer 2 switching solution, using technology from the Zarlink family to offer a highly integrated product for the unmanaged, DiffServ ready, Ethernet switching market. Nine 1/10 Media Access Controllers (MAC) provide the protocol interface into the MVTX1100. These MACs perform the required packet checks to ensure that each packet provided to the Frame Engine meets all the IEEE 802.1 standards. Data packets longer than 1518 (1522 with VLAN tag) bytes and shorter than 64 bytes are dropped and MVTX1100 has been designed to support minimum inter-frame gaps between incoming packets. The PHY addresses for the 8 RMII MACs are from 08h to 0Fh. These eight ports are denoted as ports 0 to 7. The PHY address for the uplink MAC is 10h. This port is denoted as port 8. The Frame Engine (FE) is the primary packet buffering and forwarding engine within the MVTX1100. As such, the FE controls the storage of packets in and out of the external frame buffer memory, keeps track of frame buffer availability and schedules output packet transmissions. While packet data is being buffered, the FE extracts the necessary information from each packet header and sends it to the Search Engine for processing. Search results returned to the FE ensue the scheduling of packet transmission and prioritization. When a packet is chosen for transmission, the FE reads the packet from external buffer memory and places it in the output FIFO of the output port.
2.0
Address Learning and Aging
The MVTX1100 is able to begin address learning and packet forwarding shortly after powerup has been completed. The Search Engine examines the contents of its internal Switch Database Memory for each valid packet received on an input port. Unknown source and destination MAC addresses are detected when the Search Engine does not find a match within its database. These unknown source MAC addresses are learned by creating a new entry in the switch database memory, and storing the necessary resulting information in that location. Subsequent searches to a learned destination MAC address will return the new contents of that MAC Control Table (MCT) entry. After each source address search the MCT entry aging flag is updated. MCT entries that have not been accessed during a user configurable time period (2 to 67,108 seconds) will be removed. This aging time period can be configured using the 16-bit value stored in the registers MAC Address Aging Time Low and High (MATL[7:0], MATH[7:0]). The aging period is defined by the following equation: {MATH[7:0]&MATL[7:0]} x 1024ms = Tage The aging of all MCT entries is checked once during each time period. If the MCT entry has not been utilized before the end of the next time period, it will be deleted. Note that when the system clock operates at 20 MHz, the aging period will be increased, compared with 50 MHz of system clock. One should adjust the MATH and MATHL content variable accordingly.
3.0
Quality of Service
The MVTX1100 utilizes Zarlink's architecture that provides a new level of (QoS) capability to unmanaged switch applications. Similar in operation to the QoS capabilities of other Zarlink chipset members, MVTX1100 provides two transmit queues per output port. The Frame Engine manages the output transmission queues for all the MVTX1100 ports. Once the destination address search is complete, and the switch decision is passed back to the FE, the packet is inserted into the appropriate output queue. The packet entry into the high or low priority queue is controlled by either the VLAN tag information or the Type of Service/Differentiated Service (TOS/DS) field in the IP header. Either of these priority fields can be used to select the transmission priority, and the mapping of the priority field values into either the high or low priority queue can be configured using the MVTX1100 configuration registers.
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Zarlink Semiconductor Inc.
MVTX1100
Data Sheet
If the system uses the TOS/DS field to prioritize packets, there are two choices regarding which bits of the TOS/DS field are used. Bits [0:2] of the TOS byte (known as the IP precedence field) or bits [3:5] of the TOS byte (known as the DRT field) can be used to map the transmission queue priority. Either bits, [0:2] or [3:5], can also be used as a packet drop precedence, by using bits 6 and 7 of the FCB Buffer Low Threshold register (FCBST). MVTX1100 utilizes Weighted Round Robin (WRR) and Weighted Random Early Detection/Drop (WRED) to schedule packets for transmission. To enable MVTX1100's QoS capabilities requires the use of an external EEPROM to change the default register configurations and turn on QoS. Weighted Round Robin is an efficient method to ensure that each of the transmission queues gets at least a minimum service level. With two output transmission queues, MVTX1100 will transmit "X" packets from the high priority queue before transmitting "Y" packets from the low priority queue. MVTX1100 allows the designer to set the high priority weight to a value between 0 and 16. The low priority weight is fixed at the value 1. If the high priority weight is set to the value 4, then it will transmit 4 high priority packets before transmitting each low priority packet. MVTX1100 also uses a proprietary mechanism to ensure the timely delivery of high priority packets. When the latency of high priority packets reaches a threshold, it will override the WRR weights and transmit only high priority packets until the high priority packet delays are below the threshold. This threshold limit is set at less than 1 ms (last bit in and first bit out). The QoS capabilities of the MVTX1100 are enabled by loading the appropriate values into the configuration registers. QoS for packet transmission is enabled by performing the following four steps: 1. Select the TOS/DS or VLAN Priority Tag field as the control for IP packet transmission. The selection is made using bit 7 of the Flooding Control (FCR[7]) register. FCR[7]=0, use VLAN Priority Tag field to map the transmission priority if this Tag field exists. FCR[7]=1, use TOS/DS field for IP packet transmission priority mapping.
2. Select which TOS/DS field to use as the control for packet transmission priority if the TOS/DS field was selected in step 1. The selection is made using bit 6 of the FCB Buffer Low Threshold (FCBST[6]) register. FCBST[6]=0, use DTR subfield to map the transmission priority. FCBST[6]=1, use IP precedence subfield1 to map the transmission priority.
3. Set the transmission queue weight for the high priority queue in the Transmission Scheduling Control (AXSC[3:0]) register. 4. Set the priority mappings from the TOS/DS or VLAN Priority Tag field to the high or low priority output queue. The selection is made using the VLAN Priority Map (AVPM) and TOS Priority Map (TOSPML) registers. Note that, for half duplex operation, the priority queues2 must be enabled using bit 7 in the Transmission Scheduling Control (AXSC[7]) register to utilize the QoS function. When QoS is enabled, MVTX1100 will utilize WRR to schedule packet transmission, and will use Weighted Random Early Detection/Drop (WRED) to drop random packets in order to handle buffer memory congestion. In this method, only certain packet flows are slowed down while the remaining see no impact from the network traffic congestion. Weighted Random Early Detection/Drop (WRED) is a method of handling traffic congestion in the absence of flow control mechanisms. When flow control is enabled, all devices that are connected to a switch node that is exercising flow control are effectively unable to transmit, including nodes that are not directly responsible for the congestion problem. This inability to transmit during flow control periods would play havoc with voice packets, or other high priority packet flows, and therefore flow control is not recommended for networks that mix voice and data traffic.
1. IP precedence and DTR subfields are referred to as TOS/DS[0:2] and TOS/DS[3:5] in the IP TOS/DS byte. 2. In Half Duplex mode, the QoS functions are disabled by default.
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Zarlink Semiconductor Inc.
MVTX1100
Data Sheet
WRED allows traffic to continue flowing into ports on a switch, and randomly drops packets with different probabilities based upon each packet's priority markings. As the switch congestion increases, the probability of dropping an input packet increases, and as congestion decreases, the probability of dropping an input packet decreases. In this manner, only traffic flows that have had packets dropped will be affected by the congestion. Other traffic flows will see no effect. The following table summarizes the WRED operation of the MVTX1100. It lists the buffer thresholds at which each drop probability takes effect. WRED Threshold Condition for High Priority Queue Level 0 Level 1 Level 2 Condition for Low Priority Queue Drop Percentage Drop Percentage for High-Drop Packet 50% 75% 100% Drop Percentage for Low-Drop Packet 0% 25% 50%
Total buffer space available in device is LPBT 24 buffers occupied 72 buffers occupied 84 buffers occupied
Table 1 - WRED Operation of the MVTX1100 The WRED packet drop capabilities of MVTX1100 are enabled by performing the following three steps: 1. Select the TOS/DS or VLAN Tag field as the control for packet dropping. The selection is made using bit 7 of the Flooding Control (FCR[7]) register. FCR[7]=0, use VLAN Priority Tag field to map the drop priority if this Tag field exists FCR[7]=1, use ToS/DS field for IP packet transmission priority mappin.
2. Select which TOS/DS Tag field to use for packet dropping provided that the TOS/DS field was selected in step 1. The selection is made using bit 7 of the FCB Buffer Low Threshold (FCBST[7]) register. FCBST[7]=0, use DTR subfield to map the drop priority FCBST[7]=1, use IP precedence subfield to map the drop priority
3. Set the drop mappings from the TOS/DS or VLAN Tag field to the high or low drop priority output flag. The selection is made using the VLAN Drop Map (AVDM) and TOS Discard Map (TOSDML) registers. Note that to utilize the QoS function of the MVTX1100, flow control has to be disabled.
4.0
Buffer Management
MVTX1100 stores each input packet into the external frame buffer memory while determining the destination the packet is to be forwarded to. The total number of packets that can be stored in the frame buffer memory depends upon the size of the external SBRAM that is utilized. For a 256 k byte SBRAM MVTX1100 can buffer 170 packets. For a 512 K byte SBRAM MVTX1100 can buffer 340 packets. In order to provide good QoS characteristics, MVTX1100 must allocate the available buffer space to low and high priority unicast and multicast traffic. This can be accomplished using the external EEPROM to load the appropriate values into MVTX1100 configuration registers. To allow the designer to set the minimum number of buffers provided for low drop priority unicast traffic, use the Low Drop Priority Buffer Threshold (LPBT[7:0]) register. To set the maximum number of buffers allocated for all multicast packets, use the Multicast Buffer Control (MBCR[7:0]) register. During operation MVTX1100 will continuously monitor the amount of frame buffer memory that is available, and when the unused buffer space falls below a designer configurable threshold, MVTX1100 will begin to drop incoming packets (WRED). This threshold is set using the FCB Buffer Low Threshold (FCBST[5:0]) register.
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Zarlink Semiconductor Inc.
MVTX1100
5.0 Virtual LANs
Data Sheet
MVTX1100 provides the designer the ability to define a single port-based Virtual LAN (VLAN) for each of the nine ports. This VLAN is individually defined for each port using the Port Control Registers (ECR1Px[6:4]). Bits [6:4] allow the designer to define a VLAN ID (value between 0-7) for each port. When packets arrive at an input of MVTX1100, the search engine will determine the VLAN ID for that port, and then determine which of the other ports also are members of that VLAN by matching their assigned VLAN Id values. The packet will then be transmitted to each port with the same VLAN ID as the source port.
6.0
Concentration Mode
MVTX1100 supports a Concentration Mode, where each of the 0-7 port is only allowed to directly communicate with the uplink port 8. This mode ensures that data from any of ports 0-7 cannot be directly seen by any other port. This feature is used in MDU applications to provide data privacy to subscribers. To use this mode, a CONC (concentration) bit in each ECR1 register of ports 0-8 must be enabled, i.e., ECR1 [7]=1, and ports 0-7 must each be set on a separate VLAN. Note that, in concentration mode, the VLAN of port 8 will be ignored. A more flexible concentration mode can be set up. For this mode, ports 0-7 are partitioned into several groups, sharing the same VLAN ID. This will allow traffic within the same group to freely communicate with each other, while continuing to communicate outside the group in concentration mode.
7.0
Port Trunking
Port trunking allows the designer to configure the MVTX1100, such that ports 0 and 1 are defined as a logical port. This provides a 20Mb/s link to a switch or server using two 10Mb/s ports in parallel. Ports 0 and 1 can be trunked by pulling the TRUNK_EN pin to the high state. In this mode, the source MAC address of all packets received from the trunk are checked against the MCT database to ensure that they have a port ID of 0 or 1. Packets that have a port ID other than 0 and 1 will effect the MVTX1100 to learn the new MAC address for this port change. On transmission, the selected trunk port is determined by hashing the source and destination MAC addresses. This provides a one-to-one mapping between the trunk port and the MAC addresses. Subsequent packets with the same MAC addresses will always utilize the same trunk port. MVTX1100 also provides a safe fail-over mode for port trunking. If one of the two ports goes down, via the ports link signal, MVTX1100 will switch all traffic destined to the failed port over to the remaining port in the trunk. Thus maintaining the trunk link, albeit at a lower effective bandwidth.
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Zarlink Semiconductor Inc.
MVTX1100
8.0 Port Mirroring
Data Sheet
The port mirroring function is only supported in RMII mode. Using the 4 port mirroring control pins provides the ability to enable or disable port mirroring, select which of the remaining 7 ports is to be mirrored and whether the received or transmitted data is being mirrored. The control for this function is shown in the following table. Mirrored Port Port 0 RX Port 0 TX Port 1 RX Port 1 TX Port 2 RX Port 2 TX Port 3 RX Port 3 TX Port 4 RX Port 4 TX Port 5 RX Port 5 TX Port 6 RX Port 6 TX Disabled Mirror_Control [3] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X Mirror_Control [2] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Mirror_Control [1] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 Mirror_Control [0] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
1 1 Table 2 - Port Mirroring Configuration
When enabled, port mirroring will allow the user to monitor traffic going through the switch on output Port 7. If the port mirroring control pins, Mirror_Control[3:0], are left floating, MVTX1100 will operate with the port mirroring function disabled. When port mirroring is enabled, the user must configure Port 7 to operate in the same mode as the port it is mirroring (autoneg, duplex, speed, flow control).
9.0
Power Saving Mode in MAC
The power saving mode is activated only in RMII mode. MVTX1100 was designed to be power efficient. When the internal RMII MAC sections detect that the external port is not receiving or transmitting packets, it will shut down and conserve power. When new packet data is loaded into the output transmit FIFO of a MAC in power saving mode, the MAC will return to life and begin operating immediately. When the MAC is in power saving mode and new packet data is received on the RMII interface, the MAC will return to life and receive data normally into the receive FIFO. This wake up occurs when the MAC sees the CRS_DV signal asserted. Using this method, the switch will turn off all MAC sections during periods when there is no network activity (at night for example), and save power. For large networks this power savings can be significant. To achieve the maximum power efficiency, the designer should use a physical layer transceiver that utilizes "Wake-On-LAN" technology.
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Zarlink Semiconductor Inc.
MVTX1100
10.0 EEPROM I2C Interface
Data Sheet
A simple 2 wire serial interface is provided to allow the configuration of the MVTX1100 via an external EEPROM. MVTX1100 utilizes a 1 K bit EEPROM with an I2C interface.
11.0
Management Interface
MVTX1100 uses a standard parallel port interface to provide external CPU access to the internal registers. This parallel interface consists of 3 pins: DATA0, STROBE and ACK. The DATA0 pin provides the address and data content input to MVTX1100, while the ACK pin provides the corresponding output to the external CPU. The STROBE pin is provided as the clock for both serial data streams. Any of its internal registers can be modified through this parallel port interface.
Figure 4 - Write Command
Figure 5 - Read Command Each management interface transfer consists of four parts: 1. A START pulse - occurs when DATA is sampled high when STROBE is rising followed by DATA being sampled low when STROBE falls. 2. Register Address strobed into DATA0 pin by the high level of the STROBE pin. 3. Either a Read or Write Command (see waveforms above). 4. Data to be written provided on DATA0, or data to be read back provided on ACK. Any command can be aborted in the middle by sending an ABORT pulse to MVTX1100. An ABORT pulse occurs when DATA is sampled low and STROBE is rising, then DATA is sampled high when STROBE falls.
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Zarlink Semiconductor Inc.
MVTX1100
12.0 Configuration Register Definitions
Data Sheet
MVTX1100 registers can be accessed via the parallel interface and/or the I 2C interface. Some registers are only accessible through the parallel interface. The access method for each register is listed in the individual register definitions. Each register is 8-bit wide.
12.1
* *
GCR - Global Control Register
Access: parallel interface, Write Only Address: h30 Bit 0 Bit 1 Save configuration into EEPROM Write '1' followed by a '0' Save configuration into EEPROM and reset system Write '1' (self-clearing due to reset) Start Built-In Self-Test (BIST) Write '1' followed by a '0' Reset system Write '1' (self-clearing due to reset) Reserved (Default = 0) (Default = 0)
Bit 2 Bit 3 Bit [7:4]
(Default = 0) (Default = 0)
12.2
* *
DCR - Device Status and Signature Register
Access: parallel interface, Read Only Address: h31 Bit 0 Busy writing configuration from I2C 1: Activity 0: No Activity Busy reading configuration from I2C 1: Activity 0: No Activity Built-In Self-Test (BIST) in progress 1: BIST In-Progress 0: Normal Mode RAM error during BIST 1: RAM Error 0: No Error Reserved Revision number 00: Initial Silicon 01: Second Silicon
Bit 1
Bit 2
Bit 3
Bit [5:4] Bit [7:6]
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Zarlink Semiconductor Inc.
MVTX1100
12.3
* *
Data Sheet
DA - DA Register
Access: parallel interface, Read Only Address: h36 Always returns 8-bit value hDA. Indicates the (Default DA) parallel port connection is good.
12.4
* *
MBCR - Multicast Buffer Control Register (Address H00)
Access: parallel interface and I2C, Read/Write Address: h00 Bit [7:0] MAX_CNT_LMT Maximum number of multicast frames allowed (Default = 80)
12.5
* *
FCBST - FCB Buffer Low Threshold
Access: parallel interface and I2C, Read/Write Address: h01 Bits [5:0] BUF_LOW_TH Buffer Low Threshold - number of FCB left before triggering WRED Use IP precedence field (TOS[0:2]) for Priority Use IP precedence subfield (TOS[0:2]) for Drop Note that, for Bits 6 and 7, Default = 0 means to use DTR filed (TOS[3:5]). (Default = 3F)
Bit 6 Bit 7
(Default = 0) (Default = 0)
12.6
* *
LPBT - Low Drop Priority Buffer Threshold
Access: parallel interface and I2C, Read/Write Address: h02 Bit [7:0] LOW_PRI_CNT Number of frame buffers reserved for low-dropping traffic (Default 3F)
12.7
* *
FCR - Flooding Control Register
Access: parallel interface and I2C, Read/Write Address: h03 Bits [3:0] Bits [6:4] U2MR TimeBase Unicast to Multicast Rate 000 = 100 s 001 = 200 s 010 = 400 s 011 = 800 s 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 100 s Pick TOS over VLAN priority for IP Packet. (Default = 8) (Default = 000)
Bit 7
USE_TOS
(Default = 0)
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Zarlink Semiconductor Inc.
MVTX1100
12.8
* *
Data Sheet
AVTCL - VLAN Type Code Register Loq
Access: parallel interface and I2C, Read/Write Address: h04 Bit [7:0] VLANType_LOW Lower 8 bits of VLAN type code. (Default 00)
12.9
* *
AVTCH - VLAN Type Code Register High
Access: parallel interface and I2C, Read/Write Address: h05 Bit [7:0] VLANType_HIGH Upper 8 bits of the VLAN type code (Default 81)
12.10
* *
AVPM - VLAN Priority Map
Access: parallel interface and I2C, Read/Write Address: h06 Map VLAN tag into 2 transmit queues (0 = low priority, 1 = high priority) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Mapped priority of tag value 0 Mapped priority of tag value 1 Mapped priority of tag value 2 Mapped priority of tag value 3 Mapped priority of tag value 4 Mapped priority of tag value 5 Mapped priority of tag value 6 Mapped priority of tag value 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0)
12.11
* *
AVDM - VLAN Discard Map
Access: parallel interface and I2C, Read/Write Address: h07 Map VLAN tag into frame discard when low priority buffer usage is above threshold Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Frame discard for tag value 0 Frame discard for tag value 1 Frame discard for tag value 2 Frame discard for tag value 3 Frame discard for tag value 4 Frame discard for tag value 5 Frame discard for tag value 6 Frame discard for tag value 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0)
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Zarlink Semiconductor Inc.
MVTX1100
12.12
* *
Data Sheet
TOSPML - TOS/DS Priority Map Low
Access: parallel interface and I2 C, Read/Write Address: h08 Map TOS field in IP packet into 2 transmit queues (0 = low priority, 1 = high priority). Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Mapped priority when TOS is 0 Mapped priority when TOS is 1 Mapped priority when TOS is 2 Mapped priority when TOS is 3 Mapped priority when TOS is 4 Mapped priority when TOS is 5 Mapped priority when TOS is 6 Mapped priority when TOS is 7
1
(Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0)
1. TOS = 1 means the appropriate 3-bit TOS subfield is "001.
12.13
* *
TOSDML - TOS/DS Discard Map
Access: parallel interface and I2C, Read/Write Address: h0A Map TOS into frame discard when low priority buffer usage is above threshold Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Frame discard when TOS is 0 Frame discard when TOS is 1 Frame discard when TOS is 2 Frame discard when TOS is 3 Frame discard when TOS is 4 Frame discard when TOS is 5 Frame discard when TOS is 6 Frame discard when TOS is 7 (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0) (Default 0)
12.14
* *
AXSC - Transmission Scheduling Control Register
Access: parallel interface and I2C, Read/Write Address: h0B Bits [3:0]: Bit [4] Bit [5] Bit [6]: Bit [7]: Transmission Queue Service Weight for high priority queue Reserved Reserved Global Flow Control Half Duplex Priority Enable (Default 0, enable) (Default 0) (Default F)
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Zarlink Semiconductor Inc.
MVTX1100
12.15
* *
Data Sheet
MII_OP0 - MII Register Option 0
Access by parallel interface and I2C, Read/Write Address: h0C To provide a non-standard address for the Phy Status Register. When low and high Address bytes are 0, MVTX1100 will use the standard address. Bit [7:0] Low order address byte (Default 00)
12.16
* *
MII_OP1 - MII Register Option 1
Access: parallel interface and I2C, Read/Write Address: h0D Bit [7:0] High order address byte (Default 00)
12.17
AGETIME_LOW - Mac Address Aging Timer Low
Access: parallel interface and I2C, Read/Write Address: h0E Bit [7:0] Low byte of the MAC address aging timer. (Default 25)
12.18
* *
AGETIME_HIGH - Mac Address Aging Timer High
Access: parallel interface and I2C, Read/Write Address: h0F Bit [7:0] High byte of the MAC address aging timer. The aging time is based on the following formula: {AGETIME_HIGH, AGETIME_LOW} x 1024 ms. (Default 01)
12.19
* *
ECR1P0 - Port 0 Control Register
Access: parallel interface and I2C, Read/Write Address: h10 Bits [3:0] Bit [0] Bit [1] Bit [2] Bit [3] RMII Port Mode Only for RMII mode, Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bits [2:0] 0 - Auto and advertise based on Bits [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0000)
Bits [6:4] Bit [7]
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Zarlink Semiconductor Inc.
MVTX1100
12.20
* *
Data Sheet
ECR1P1 - Port 1 Control Register
Access: parallel interface and I2C, Read/Write Address: h11 Bits [3:0] Bit [0] Bit [1] Bit [2] Bit [3] RMII Port Mode Only for RMII mode, Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bits [2:0] 0 - Auto and advertise based on Bits [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bits [6:4] Bit [7]
12.21
* *
ECR1P2 - Port 2 Control Register
Access: parallel interface and I2C, Read/Write Address: h12 Bits [3:0] RMII Port Mode Only for RMII mode,(Default 0000) Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bits [2:0] 0 - Auto and advertise based on Bits [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bit [0] Bit [1] Bit [2] Bit [3]
Bits [6:4] Bit [7]
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Zarlink Semiconductor Inc.
MVTX1100
12.22
* *
Data Sheet
ECR1P3 - Port 3 Control Register
Access: parallel interface and I2C, Read/Write Address: h13 Bits [3:0] Bit [0] Bit [1] Bit [2] Bit [3] RMII Port Mode Only for RMII mode, Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bits [2:0] 0 - Auto and advertise based on Bits [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bits [6:4] Bit [7]
12.23
* *
ECR1P4 - Port 4 Control Register
Access: parallel interface and I2C, Read/Write Address: h14 Bits [3:0] RMII Port Mode Only for RMII mode, (Default 0000) Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bit [2:0] 0 - Auto and advertise based on Bit [2:0] PVID Reserved Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bit [0] Bit [1] Bit [2] Bit [3]
Bits [6:4] Bit [7]
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Zarlink Semiconductor Inc.
MVTX1100
12.24
* *
Data Sheet
ECR1P5 - Port 5 Control Register
Access: parallel interface and I2C, Read/Write Address: h15 Bits [3:0] Bit [0] Bit [1] Bit [2] Bit [3] RMII Port Mode Only for RMII mode, Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bit [2:0] 0 - Auto and advertise based on Bits [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bits [6:4] Bit [7]
12.25
* *
ECR1P6 - Port 6 Control Register
Access: parallel interface and I2C, Read/Write Address: h16 Bits [3:0] Bit [0] Bit [1] Bit [2] Bit [3] RMII Port Mode Only for RMII mode, Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bit [2:0] 0 - Auto and advertise based on Bit [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bits [6:4] Bit [7]
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Zarlink Semiconductor Inc.
MVTX1100
12.26
* *
Data Sheet
ECR1P7 - Port 7 Control Register
Access: parallel interface and I2C, Read/Write Address: h17 Bits [3:0] Bit [0] Bit [1] Bit [2] Bit [3] RMII Port Mode Only for RMII mode, Serial Mode DON'T CARE 1 - Flow Control Off 0 - Flow Control On 1 - Half Duplex 0 - Full Duplex 1 - 10 Mbps 0 - 100 Mbps 1 - Force configuration based on Bit [2:0] 0 - Auto and advertise based on Bit [2:0] PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bits [6:4] Bit [7]
12.27
* *
ECR1P8 - Port 8 Control Register
Access: parallel interface and I2C, Read/Write Address: h18 Bits [3:0] Bit [3] Port Mode 1 - Force configuration based on Bit [2:0] 0 - Autonegotiate and advertise based on Bit[2:0] 1 - 10 Mbps 0 - 100 Mbps 1 - Half Duplex 0 - Full Duplex 1 - Flow Control Off 0 - Flow Control On PVID CONC: Port-based VLAN ID Enable Concentration Mode (Default 000) (Default 0) (Default 0000)
Bit [2] Bit [1] Bit [0] Bits [6:4] Bit [7]
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Zarlink Semiconductor Inc.
MVTX1100
12.28
* *
Data Sheet
FC_0 - Flow Control Byte 0
Access: parallel interface and I2C, Read/Write Address: h19 The flow control hold time parameter is the length of time a flow control message is effectual (i.e. halts incoming traffic) after being received. The hold time is measured in units of "slots," the time it takes to transmit 64 bytes at wire speed. The default setting is 32 slots, or for a 100 Mbps port, approximately 164 s. Bits [7:0] Flow control hold time byte 0 (Default FF)
12.29
* *
FC_1 - Flow Control Byte 1
Access: parallel interface and I2C, Read/Write Address: h1A Bits [7:0] Flow control hold time byte 1 (Default 00)
12.30
* *
FC_2 - Flow Control CRC Byte 0
Access: parallel interface and I2C, Read/Write Address: h1B Bits [7:0] Flow control frame CRC byte 0 (Default 96)
12.31
* *
FC_3 - Flow Control CRC Byte 1
Access: parallel interface and I2C, Read/Write Address: h1C Bits [7:0] Flow control frame CRC byte 1 (Default 8E)
12.32
* *
FC_4 - Flow Control CRC Byte 2
Access: parallel interface and I2C, Read/Write Address: h1D Bits [7:0] Flow control frame CRC byte 2 (Default 99)
12.33
* *
FC_5 - Flow Control CRC Byte 3
Access: parallel interface and I2C, Read/Write Address: h1E Bits [7:0] Flow control frame CRC byte 3 (Default 9A)
12.34
* *
CHECKSUM - EEPROM Checksum
* Access: parallel interface and I2C, Read/Write * Address: h24 The calculation is [0x100 - ((sum of registers 0x00~0x23) & 0xFF)]. For example, based on the default register settings, the CHECKSUM value would be 0xEE. Bits [7:0] Checksum (Default 00)
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Zarlink Semiconductor Inc.
MVTX1100
13.0 MVTX1100 Pin Descriptions
Note: # Active low signal I Input signal S Input signal with Schmitt-Trigger O Output signal OD Open-Drain driver I/O Input & Output signal SL Slew Rate Controlled D Pulldown U Pullup 5 5V Tolerance Symbol Type Name & Functions
Data Sheet
Pin No(s). Frame Buffer Memory Interface 201, 200, 199, 197, 196, 195, 193, 192, 191, 190, 188, 187, 186, 185, 183, 182, 181, 179, 178, 177, 176, 174, 173, 172, 170, 169, 168, 167, 165, 164, 163, 161 203, 151, 158, 160, 10, 9, 8, 6, 5, 4, 2, 1, 208, 206, 205, 204, 150 153 155 156 157 MII Management Interface 120 122
L_D[31:0]
I/O, U, SL
Databus to Frame Buffer Memory
L_A[18:2]
I/O, U, SL
Address Pins for Buffer Memory
L_CLK L_WE# L_OE# L_ADSC#
O O, SL O O, SL
Frame Buffer Memory Clock Frame Buffer Memory Write Enable Frame Buffer Memory Output Enable Address Status Control
M_MDC M_MDIO
O I/O, U
MII Management Data Clock MII Management Data I/O
I2C Interface (Serial EEPROM Interface) 123 124 SCL SDA O, U, 5 I/O, U, OD, 5 I2C Data Clock I2C Data I/O
Parallel Port Management Interface 127 128 129 Port 0 Serial Interface 23 M0_RXD I, U Port 0 Receive Data STROBE DATA0 ACK I, U, S, 5 I, U, 5 O, U, OD, 5 Strobe Pin Data Pin Acknowledge Pin
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Zarlink Semiconductor Inc.
MVTX1100
Pin No(s). 24 22 20 21 19 12 13 14 Port 1 Serial Interface 30 31 29 27 28 26 15 16 17 Port 2 Serial Interface 37 38 36 34 35 33 47 48 49 Port 3 Serial Interface 44 M3_RXD I, U Port 3 Receive Data M2_RXD M2_RXCLK M2_CRS_DV M2_TXD M2_TXCLK M2_TXEN M2_CLS M2_LINK M2_DUPLEX I, U I, U I, D O I O I, U I, U I, U` Port 2 Receive Data Port 2 Receive Clock M1_RXD M1_RXCLK M1_CRS_DV M1_TXD M1_TXCLK M1_TXEN M1_CLS M1_LINK M1_DUPLEX I, U I, U I, D O I O I, U I, U I, U Port 1 Receive Data Port 1 Receive Clock Symbol M0_RXCLK M0_CRS_DV M0_TXD M0_TXCLK M0_TXEN M0_CLS M0_LINK M0_DUPLEX I, U I, D O I O I, U I, U I, U Type Name & Functions Port 0 Receive Clock
Data Sheet
Port 0 Carrier Sense and Data Valid Port 0 Transmit Data Port 0 Transmit Clock Port 0 Transmit Enable Port 0 Collision Detection Port 0 Link Status Port 0 Full Duplex Select (half-duplex = 0)
Port 1 Carrier Sense and Data Valid Port 1 Transmit Data Port 1 Transmit Clock Port 1 Transmit Enable Port 1 Collision Detection Port 1 Link Status Port 1 Full-Duplex Select (half-duplex = 0)
Port 2 Carrier Sense and Data Valid Port 2 Transmit Data Port 2 Transmit Clock Port 2 Transmit Enable Port 2 Collision Detection Port 2 Link Status Port 2 Full-Duplex Select (half-duplex = 0)
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Zarlink Semiconductor Inc.
MVTX1100
Pin No(s). 45 43 41 42 40 50 51 52 Port 4 Serial Interface 64 65 63 61 62 60 53 54 55 Port 5 Serial Interface 71 72 70 68 69 67 56 57 58 Port 6 Serial Interface 78 M6_RXD I, U Port 6 Receive Data M5_RXD M5_RXCLK M5_CRS_DV M5_TXD M5_TXCLK M5_TXEN M5_CLS M5_LINK M5_DUPLEX I, U I, U I, D O I O I, U I, U I, U Port 5 Receive Data Port 5 Receive Clock M4_RXD M4_RXCLK M4_CRS_DV M4_TXD M4_TXCLK M4_TXEN M4_CLS M4_LINK M4_DUPLEX I, U I, U I, U O I O I, U I, U I, U Port 4 Receive Data Port 4 Receive Clock Symbol M3_RXCLK M3_CRS_DV M3_TXD M3_TXCLK M3_TXEN M3_CLS M3_LINK M3_DUPLEX I, U I, D O I O I, U I, U I, u Type Name & Functions Port 3 Receive Clock
Data Sheet
Port 3 Carrier Sense and Data Valid Port 3 Transmit Data Port 3 Transmit Clock Port 3 Transmit Enable Port 3 Collision Detection Port 3 Link Status Port 3 Full-Duplex Select (half-duplex = 0)
Port 4 Carrier Sense and Data Valid Port 4 Transmit Data Port 4 Transmit Clock Port 4 Transmit Enable Port 4 Collision Detection Port 4 Link Status Port 4 Full-Duplex Select (half-duplex = 0)
Port 5 Carrier Sense and Data Valid Port 5 Transmit Data Port 5 Transmit Clock Port 5 Transmit Enable Port 5 Collision Detection Port 5 Link Status Port 5 Full-Duplex Select (half-duplex = 0)
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Zarlink Semiconductor Inc.
MVTX1100
Pin No(s). 79 77 75 76 74 88 89 90 Port 7 Serial Interface 85 86 84 82 83 81 91 92 93 Port 0 RMII Interface 24, 23 22 21, 20 19 Port 1 RMII Interface 31, 30 29 28, 27 26 Port 2 RMII Interface 38, 27 M2_RXD[1:0] I, U Port 2 Receive Data M1_RXD[1:0] M1_CRS_DV M1_TXD[1:0] M1_TXEN I, U I, D O O Port 1 Receive Data M0_RXD[1:0] M0_CRS_DV M0_TXD[1:0] M0_TXEN I, U I, D O O Port 0 Receive Data M7_RXD M7_RXCLK M7_CRS_DV M7_TXD M7_TXCLK M7_TXEN M7_CLS M7_LINK M7_DUPLEX I, U I, U I, D O I O U I, U I, U Port 7 Receive Data Port 7 Receive Clock Symbol M6_RXCLK M6_CRS_DV M6_TXD M6_TXCLK M6_TXEN M6_CLS M6_LINK M6_DUPLEX I, U I, D O I O I, U I, U I, U Type Name & Functions Port 6 Receive Clock
Data Sheet
Port 6 Carrier Sense and Data Valid Port 6 Transmit Data Port 6 Transmit Clock Port 6 Transmit Enable Port 6 Collision Detection Port 6 Link Status Port 6 Full-Duplex Select (half-duplex = 0)
Port 7 Carrier Sense and Data Valid Port 7 Transmit Data Port 7 Transmit Clock Port 7 Transmit Enable Port 7 Collision Detection Port 7 Link Status Port 7 Full-Duplex Select (half-duplex = 0)
Port 0 Carrier Sense and Data Valid Port 0 Transmit Data Port 0 Transmit Enable
Port 1 Carrier Sense and Data Valid Port 1 Transmit Data Port 1 Transmit Enable
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Zarlink Semiconductor Inc.
MVTX1100
Pin No(s). 36 35, 34 34 Port 3 RMII Interface 45, 44 43 42, 41 40 Port 4 RMII Interface 65, 64 63 62, 61 60 Port 5 RMII Interface 72, 71 70 69, 68 67 Port 6 RMII Interface 79, 78 77 76, 75 74 Port 7 RMII Interface 86, 85 84 83, 82 81 Port 8 MII Interface 105, 104, 103, 102 M8_RXD[3:0] I, U Port 8 Receive Data M7_RXD[1:0] M7_CRS_DV M7_TXD[1:0] M7_TXEN I, U I, D O O Port7 Receive Data M6_RXD[1:0] M6_CRS_DV M6_TXD[1:0] M6_TXEN I, U I, D O O Port 6 Receive Data M5_RXD[1:0] M5_CRS_DV M5_TXD[1:0] M5_TXEN I, U I, D O O Port 5 Receive Data M4_RXD[1:0] M4_CRS_DV M4_TXD[1:0] M4_TXEN I, U I, D O O Port 4 Receive Data M3_RXD[1:0] M3_CRS_DV M3_TXD[1:0] M3_TXEN I, U I, D O O Port 3 Receive Data Symbol M2_CRS_DV M2_TXD[1:0] M2_TXEN I, D O O Type Name & Functions
Data Sheet
Port 2 Carrier Sense and Data Valid Port 2 Transmit Data Port 2 Transmit Enable
Port 3 Carrier Sense and Data Valid Port 3 Transmit Data Port 3 Transmit Enable
Port 4 Carrier Sense and Data Valid Port 4 Transmit Data Port 4 Transmit Enable
Port 5 Carrier Sense and Data Valid Port 5 Transmit Data Port 5 Transmit Enable
Port 6 Carrier Sense and Data Valid Port 6 Transmit Data Port 6 Transmit Enable
Port 7 Carrier Sense and Data Valid Port 7 Transmit Data Port 7 Transmit Enable
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Zarlink Semiconductor Inc.
MVTX1100
Pin No(s). 113, 112, 111, 110 109 97 100 107 114 116 115 98 118 Port 8 Serial Interface 102 100 97 110 107 109 98 114 115 Miscellaneous Control Pins 95 148 126 142 141 146, 145, 144, 143 M_CLK SCLK TRUNK_EN RESIN# RESETOUT# MIR_CTL[3:0] I I I, D I, S O I/O, U S8_RXD S8_RXCLK S8_CRS_DV S8_TXD S8_TXCLK S8_TXEN S8_COL S8_LINK S8_DUPLEX I, U I, U I, D O I O I, U I, U I, U Port 8 Serial Receive Data Port 8 Serial Receive Clock Symbol M8_TXD[3:0] M8_TXEN M8_RXDV M8_RXCLK M8_TXCLK M8_LINK M8_SPEED M8_DUPLEX M8_COL M8_REFCLK O O I, D I, U I/O, U I, U I/O, U I, U I, U O, U Type Name & Functions Port 8 Transmit Data Port 8 Transmit Enable Port 8 Receive Data Valid Port 8 Receive Clock Port 8 Transmit Clock Port 8 Link Status Port 8 Speed Select (100Mb = 1)
Data Sheet
Port 8 Full-Duplex Select (half-duplex = 0) Port 8 Collision Detect Port 8 Reference Clock M8_REFCLK=1/2 M_CLK
Port 8 Serial Carrier Sense and Data Valid Port 8 Serial Transmit Data Port 8 Serial Transmit Clock Port 8 Serial Transmit Enable Port 8 Serial Collision Detect Port 8 Link Status Port 8 Full-Duplex Select (half-duplex = 0)
Reference Clock for Serial interface = 50 MHz50 ppm System Clock (50 - 80 MHz) Port Trunking Enable Reset Pin PHY Reset Pin Port Mirroring Control (only for RMII mode)
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Zarlink Semiconductor Inc.
MVTX1100
Pin No(s). Test Pins 125 139 TEST# TMODE# I/O, U Manufacturing Pin. Leave as No Connect (NC) Symbol Type Name & Functions
Data Sheet
Manufacturing Pin. Puts device into test mode for ATE test. Leave as No Connect (NC) Test Outputs Test Outputs
138, 137, 136, 135 134, 133, 132, 131 Power Pins 3, 39, 73, 96, 130, 159, 184
TSTOUT[7:4] TSTOUT[3:0]
O I/O, U
VDD (Core)
Input Input Input Input
+3.3 Volt DC Supply for Core Logic (7 pins) +3.3 Volt DC Supply for I/O Pads (13 pins) Ground for Core Logic (7 pins) Ground for I/O Pads (13 pins)
11, 25, 59, 87, 101, 108, 119, VDD 147, 152, 166, 175, 194, 202 18, 46, 80, 106, 140, 171, 198 VSS (Core)
7, 32, 66, 94, 99, 117, 121, VSS 149, 154, 162, 180, 189, 207
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Zarlink Semiconductor Inc.
MVTX1100
13.1 STRAP Options
Data Sheet
The Strap options are relevant during the initial power-on period, when reset is asserted. During reset, MVTX1100 will examine the boot strap address pin to determine its value and modify the internal configuration of the chip accordingly. "1" means Pull Up "0" means Pull Down with an external 1 K Ohm Default value is 1, (all boot strap pins have internal pull up resistor). Pin No(s) 206 (L_A[5]) 208 (L_A [6]) 1 (L_A [7]) 5, 4 (L_A [10:9]) Symbol Memory Size EEPROM MII Management via MDIO XLINK Speed Name & Functions 1 - Memory size = 256 KB, 0 - Memory size = 512 KB 1 - NO EEPROM Installed 0 - EEPROM Installed1 1 - Enable 0 - Disable 11 - 100 Mbps 10 - 200 Mbps 01 - 300 Mbps 00 - 400 Mbps (0 - Pull down, 1 - Pull up) 1 - RMII Mode for ports 0-7 0 - Serial mode for ports 0-7 1 - MII Mode for port 8 0 - Serial mode for port 8 Link Polarity for serial interface 1 - Active Low 0 - Active High Full/Half Duplex Polarity for serial interface 1 - Active Low 0 - Active High Speed polarity for serial interface 1 - Active Low 0 - Active High Use in cascade mode only For Board/System Manufacturing Test2 1 - Disable 0 - Enable
160 (L_A[15]) 151 (L_A[17]) 150 (L_A[2])
Ports 0-7 RMII/Serial Port 8 MII/Serial Link Polarity
204 (L_A[3])
FDX Polarity
205 (L_A[4])
SPD100 Polarity
2 (L_A[8]) 133 (TST[2])
Device ID SBRAM Self Test
Note 1:
1. If the MVTX1100 is configured from EEPROM preset (L_A[6] pulled down at reset), it will try to load its configuration from the EEPROM. If the EEPROM is blank or not preset, it will not boot up. The parallel port can be used to program the EEPROM at any time. During normal power-up the MVTX1100 will run through an external SBRAM memory test to ensure that there are no memory interface problems. If a problem is detected, the chip will stop functioning. To facilitate board debug in the event that a system stops functioning, the MVTX1100 can be put into a continuous SBRAM self test mode to allow an operator to determine if there are stuck pins in the memory interface (using network analyzer).
Note 2:
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Zarlink Semiconductor Inc.
MVTX1100
14.0
14.1
Data Sheet
DC Electrical Characteristics
Absolute Maximum Ratings
-65C to +150C -40C to +85C +125C +3.0 V to +3.6 V -0.5 V to (VDD + 3.3 V) -0.5 V to (VDD + 0.3 V)
Storage Temperature Operating Temperature Maximum Junction Temperature Supply Voltage VDD with Respect to VSS Voltage on 5V Tolerant Input Pins Voltage on Other Pins
Caution: Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability.
14.2
DC Electrical Characteristics
VDD = 3.0 V to 3.6 V (3.3v +/- 10%) TAMBIENT = -40C to +85C
14.3
Recommended Operating Conditions
Parameter Description Frequency of Operation Supply Current - @ 55 MHz, 8x100 M, 100% Full Duplex Traffic (VDD = 3.3V) Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5 V tolerant) Input Low Voltage (TTL 5 V tolerant) Input Leakage Current (0.1 V < VIN < VDD) (all pins except those with internal pull-up/ pulldown resistors) Output Leakage Current (0.1 V < VOUT < VDD) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2 m/s air flow Thermal resistance between junction and case 2.4 0.4 2.0 VDD + 2.0 0.8 10 Min. 50 Typ. 66 580 Max. 80 Unit MHz mA V V V V A fOSC IDD VOH VOL
Symbol
VIH-TTL VIL-TTL IIL
IOL CIN COUT CI/O ja ja ja jc
10 5 5 7 29.7 28.8 26.8 12.6
A pF pF pF C/W C/W C/W C/W
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Zarlink Semiconductor Inc.
MVTX1100
14.4 Clock Frequency Specifications
Parameter SCLK - Core System Clock Input M_CLK - RMII Port Clock M8_REFCLK - MII Reference Clock L_CLK - Frame Buffer Memory Clock M_MDC - MII Management Data Clock SCL - I C Data Clock
2
Data Sheet
Symbol C1 C2 C3 C4 C5 C6
(Hz) 50 M 50 M 25 M 50 M 1.56 M 50 K
Note:
L_CLK = SCLK M_MDC = SCLK/32 SCL = M_CLK/1000
Suggestion Clock rate for various configurations: Input Configuration Port 0-7 10 M RMII 100 M RMII 100 M RMII 100 M RMII 100 M RMII 100 M RMII Port 8 10/100 M MII Not Used 10/100 M MII 200 M MII 300 M MII 400 M MII SCLK 50 M 55 M 60 M 66.66 M 75 M 80 M M_CLK (RMII) 50 M 50 M 50 M 50 M 50 M 50 M M8_REF ---50 M 75 M 100 M L_CLK =SCLK =SCLK =SCLK =SCLK =SCLK =SCLK Output M_MDC =SCLK/32 =SCLK/32 =SCLK/32 =SCLK/32 =SCLK/32 =SCLK/32 SCL 50 K 50 K 50 K 50 K 50 K 50 K
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Zarlink Semiconductor Inc.
MVTX1100
15.0
15.1
Data Sheet
AC Timing Characteristics
Frame Buffer Memory Interface:
L_D[31:0]
Figure 6 - Framer Buffer Memory Interface Timing 50 MHz Min. (ns) 5 0 1 1 1 1 1 8 8 8 8 8 CL = 30 pF CL = 50 pF CL = 50 pF CL = 30 pF CL = 30 pF Max. (ns)
Symbol L1 L2 L3 L4 L6 L8 L9
Parameter L_D[31:0] input setup time L_D[31:0] input hold time L_D[31:0] output valid delay L_A[18:2] output valid delay L_ADSC# output valid delay L_WE# output valid delay L_OE# output valid delay
Note
Table 3 - Frame Buffer Memory Interface Timing
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Zarlink Semiconductor Inc.
MVTX1100
15.2 Serial Timing Requirements
50 MHz Min. (ns) Max. (ns)
Data Sheet
Symbol M1 M2 M3 M4 M5 M6 M7
Parameter M_[8:0]_[TX/RX]CLK M[8:0]_RXD input setup time M[8:0]_RXD input hold time M[8:0]_CRS_DV input setup time M[8:0]_TXEN output delay time M[8:0]_TXD output delay time M[8:0]_LINK input setup time
Note: Serial Input Clock
4 1 4 1 1 4 11 11 CL = 30 pF CL = 30 pF
Table 4 - Serial Timing Requirements
15.3
RMII Timing Requirements
50 MHz Min. (ns) Max. (ns)
Symbol M1 M2 M3 M4 M5 M6 M7 M_CLK
Parameter
Note: Reference Input Clock
M[7:0]_RXD[1:0] input setup time M[7:0]_RXD[1:0] input hold time M[7:0]_CRS_DV input setup time M[7:0]_TXEN output delay time M[7:0]_TXD[1:0] output delay time M[7:0]_LINK input setup time
4 1 4 1 1 4 11 11 CL = 30 pF CL = 30 pF
Table 5 - RMII Timing Requirements
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Zarlink Semiconductor Inc.
MVTX1100
15.4 MII Timing Requirements
Data Sheet
Figure 7 - Transmit Timing
Symbol 1 2 3 4 5 6
Parameter M8_TXCLK rise to M8_TXD[3:0] inactive delay M8_TXCLK rise to M8_TXD[3:0] active delay M8_TXCLK rise to M8_TXEN active delay M8_TXCLK rise of last M8_TXD bit to M8_TXEN inactive delay M8_TXCLK high wide M8_TXCLK low wide M8_TXCLK input rise time require M8_TXCLK input fall time require
Time Min. 5 5 5 5 25 25 Max. 20 20 20 20 Inf. Inf. 5 5
Unit ns ns ns ns ns ns ns ns
*Inf. = infinite
Table 6 - Transmit Timing Requirements
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Zarlink Semiconductor Inc.
MVTX1100
Data Sheet
Figure 8 - Receive Timing
Symbol 1 2 3 4 5 6 7 8 9 10
Parameter M8_RXD[3:0] low input setup time M8_RXD[3:0] low input hold time M8_RXD[3:0] high input setup time M8_RXD[3:0] high input hold time M8_RXDV low input setup time M8_RXDV low input hold time M8_RXDV high input setup time M8_RXDV high input hold time M8_RXCLK high wide M8_RXCLK low wide M8_RXCLK input rise time require M8_RXCLK input fall time require
Time Min. 10 5 10 5 10 5 10 5 25 25 Inf. Inf. 5 5 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Table 7 - Receive Timing Requirements
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Zarlink Semiconductor Inc.
D D1
= 0-7
A A2 A1
E1
E
L INDEX CORNER PIN 1
Notes: 1. Pin 1 indicator may be a corner chamfer, dot or both. 2. Controlling dimensions are in millimeters. 3. The top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 4. Dimension D1 and E1 do not include mould protusion.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes:
ISSUE ACN DATE APPRD.
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